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ltc2758 1 2758fa for more information www.linear.com/ltc2758 typical application features applications description dual serial 18-bit softspan i out dacs the lt c ? 2758 is a dual 18-bit multiplying serial-input, current-output digital-to-analog converter. ltc2758a provides full 18-bit performance (inl and dnl of 1lsb maximum) over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. this softspan? dac operates from a single 3v to 5v supply and offers six output ranges (up to 10v) that can be programmed through the 3-wire spi serial interface or pin-strapped for operation in a single range. any on-chip register (including dac output-range set - tings) can be read for veriication in just one instruction cycle; and if you change register content, the altered register will be automatically read back during the next instruction cycle. voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and clr pin both reset the dac outputs to 0v regardless of output range. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. dual 18-bit v out dac with software-selectable ranges n maximum 18-bit inl error: 1 lsb over temperature n program or pin-strap six output ranges: 0v to 5v, 0v to 10v, ?2.5v to 7.5v, 2.5v, 5v, 10v n guaranteed monotonic over temperature n glitch impulse 0.4nv s (3v), 2nv s (5v) n 18-bit settling time: 2.1s n 2.7v to 5.5v single supply operation n 1a maximum supply current n voltage-controlled offset and gain trims n serial interface with readback of all registers n clear and power-on-reset to 0v regardless of output range n 48-pin 7mm 7mm lqfp package n instrumentation n medical devices n automatic test equipment n process control and industrial automation ltc2758 integral nonlinearity code 0 65536 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.60.4 0.2 0 0.8 1.0 131072 196608 262143 2758 ta01b 0v to 10v range ltc2758 5v 4 spi with readback gnd v dd ?+ +? dac b dac a reference5v v outa v outb r ina r efa reference5v refb r ofsa ge adja ge adjb r ofsb r comb r coma r inb v osadja v osadjb i out1a i out2a i out1b i out2b r fba r fbb ?+ +? 2758 ta01a lt1012 lt1012 lt1468 lt1468 0.1f offset a adjustoffset b adjust gain a adjust gain b adjust 27pf27pf downloaded from: http:///
ltc2758 2 2758fa for more information www.linear.com/ltc2758 absolute maximum ratings i out1x , i out2x to gnd ............................................ 0.3v r inx , r comx , refx, r fbx , r ofsx , v osadjx , ge adjx to gnd ....................................................... 18v v dd to gnd .................................................. C0.3v to 7v digital inputs to gnd ................................... C0.3v to 7v digital outputs to gnd ..... C0.3v to v dd +0.3v (max 7v) operating temperature range ltc2758c ................................................ 0c to 70c ltc2758i ............................................. C40c to 85c maximum junction temperature .......................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c order information lead free finish part marking* package description temperature range ltc2758bclx#pbf ltc2758lx 48-lead (7mm 7mm) plastic lqfp 0c to 70c ltc2758bilx#pbf ltc2758lx 48-lead (7mm 7mm) plastic lqfp C40c to 85c ltc2758aclx#pbf ltc2758lx 48-lead (7mm 7mm) plastic lqfp 0c to 70c ltc2758ailx#pbf ltc2758lx 48-lead (7mm 7mm) plastic lqfp C40c to 85c consult ltc marketing for parts speciied with wider operating temperature ranges. *the temperature grade is identiied by a label on the shipping container. consult ltc marketing for information on non-standard lead based inish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ pin configuration (notes 1, 2) 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 ref aref a r coma ge adja r ina r ina gnd i out2as i out2af gnd cs /ld sdi 1314 15 16 17 18 19 20 21 22 23 24 sck sro gnd v dd gndgnd clr rflag dnc m-span s0s1 4847 46 45 44 43 42 41 40 39 38 37 r ofsa r ofsa r fba r fba i out1a v osadja v osadjb i out1b r fbb r fbb r ofsb r ofsb ref bref b r comb ge adjb r inb r inb gndi out2bs i out2bf gndldac s2 top view lx package 48-lead (7mm 7mm) plastic lqfp t jmax = 150c, ja = 53c/w downloaded from: http:///
ltc2758 3 2758fa for more information www.linear.com/ltc2758 electrical characteristics v dd = 5v, v(r inx ) = 5v unless otherwise speci?ed. the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. symbol parameter conditions ltc2758b ltc2758a units min typ max min typ max static performance resolution l 18 18 bits monotonicity l 18 18 bits dnl differential nonlinearity l 1 0.2 1 lsb inl integral nonlinearity l 2 0.5 1 lsb ge gain error all output ranges l 48 6 32 lsb gain error temperature coeficient ? gain/ ? temp 0.25 0.25 ppm/c bze bipolar zero error all bipolar ranges l 36 1 24 lsb bipolar zero temperature coeficient 0.2 0.2 ppm/c unipolar zero-scale error unipolar ranges (note 3) l 0.03 3.2 0.03 3.2 lsb psr power supply rejection v dd = 5v, 10% v dd = 3v, 10% l l 1.6 4 0.1 0.3 0.8 2 lsb/v lsb/v i lkg i out1 leakage current t a = 25c t min to t max l 0.05 2 5 0.05 2 5 na na symbol parameter conditions min typ max units analog pins reference inverting resistors (note 4) l 16 20 k r ref dac input resistance (notes 5, 6) l 8 10 k r fb feedback resistors (note 6) l 8 10 k r ofs bipolar offset resistors (note 6) l 16 20 k r vosadj offset adjust resistors l 1024 1280 k r geadj gain adjust resistors l 2048 2560 k c iout1 output capacitance full-scale zero-scale 90 40 pf dynamic performance output settling time span code = 0000, 10v step. to 0.0004% fs (note 7) 2.1 s glitch impulse v dd = 5v (note 8) v dd = 3v (note 8) 2 0.4 nv?s nv?s digital-to-analog glitch impulse v dd = 5v (note 9) v dd = 3v (note 9) 2.6 0.6 nv?s nv?s reference multiplying bw 0v to 5v range, code = full scale, C3db bandwidth 1 mhz multiplying feedthrough error 0v to 5v range, v ref = 10v, 10khz sine wave 0.4 mv analog crosstalk (note 10) C109 db thd total harmonic distortion (note 11) multiplying C110 db output noise voltage density (note 12) at i out1 13 nv/ hz v dd = 5v, v(r inx ) = 5v unless otherwise speci?ed. the l denotes speci?cations that apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. downloaded from: http:///
ltc2758 4 2758fa for more information www.linear.com/ltc2758 timing characteristics the l denotes speci?cations that apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. electrical characteristics v dd = 5v, v(r inx ) = 5v unless otherwise speci?ed. the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. symbol parameter conditions min typ max units power supplyv dd supply voltage l 2.7 5.5 v i dd v dd supply current digital inputs = 0v or v dd l 0.5 2 a digital inputsv ih digital input high voltage 3.3v v dd 5.5v 2.7v v dd < 3.3v l l 2.4 2 v v v il digital input low voltage 4.5v < v dd 5.5v 2.7v v dd 4.5v l l 0.8 0.6 v v hysteresis voltage 0.1 v i in digital input current v in = gnd to v dd l 1 a c in digital input capacitance v in = 0v (note 13) l 6 pf digital outputsv oh i oh = 200a 2.7v v dd 5.5v l v dd C 0.4 v v ol i ol = 200a 2.7v v dd 5.5v l 0.4 v symbol parameter conditions min typ max units v dd = 4.5v to 5.5v t 1 sdi valid to sck set-up l 7 ns t 2 sdi valid to sck hold l 7 ns t 3 sck high time l 11 ns t 4 sck low time l 11 ns t 5 cs /ld pulse width l 9 ns t 6 lsb sck high to cs /ld high l 4 ns t 7 cs /ld low to sck positive edge l 4 ns t 8 cs /ld high to sck positive edge l 4 ns t 9 sro propagation delay c load = 10pf l 18 ns t 10 clr pulse width low l 36 ns t 11 ldac pulse width low l 15 ns t 12 clr low to rflag low c load = 10pf (note 13) l 50 ns t 13 cs /ld high to rflag high c load = 10pf (note 13) l 40 ns sck frequency 50% duty cycle (note 14) l 40 mhz v dd = 2.7v to 3.3v t 1 sdi valid to sck set-up l 9 ns t 2 sdi valid to sck hold (note 13) l 9 ns t 3 sck high time c l = 10pf l 15 ns t 4 sck low time l 15 ns t 5 cs /ld pulse width l 12 ns t 6 lsb sck high to cs /ld high l 5 ns downloaded from: http:///
ltc2758 5 2758fa for more information www.linear.com/ltc2758 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the speciied maximum operating junction temperature may impair device reliability. note 3 : calculation from feedback resistance and i out1 leakage current speciications; not production tested. in most applications, unipolar zero- scale error is dominated by contributions from the output ampliier. note 4: input resistors measured from r inx to r comx ; feedback resistors measured from r comx to refx. note 5: dac input resistance is independent of code. note 6: parallel combination of the resistances from the speciied pin to i out1x and from the speciied pin to i out2x . note 7: using lt1468 with c feedback = 27pf. a 0.0004% settling time of 1.8s can be achieved by optimizing the time constant on an individual basis. see application note 120, 1ppm settling time measurement for a monolithic 18-bit dac . timing characteristics the l denotes speci?cations that apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. note 8: measured at the major carry transition, 0v to 5v range. output ampliier: lt1468; c fb = 50pf. note 9: full-scale transition; ref = 0v. note 10: analog crosstalk is deined as the ac voltage ratio v outb /v refa , expressed in db. refb is grounded, and dac b is set to 0v-5v span and zero-, mid- or full- scale code. v refa is a 3v rms , 1khz sine wave. note 11: ref = 6v rms at 1khz. 0v to 5v range. dac code = fs. output ampliier = lt1468. note 12: calculation from v n = 4ktrb , where k = 1.38e-23 j/k (boltzmann constant), r = resistance (), t = temperature (k), and b = bandwidth (hz). 0v to 5v range; zero-, mid-, or full-scale. note 13: guaranteed by design; not production tested. note 14: when using sro, maximum sck frequency f max is limited by sro propagation delay t 9 as follows: f max = 1 2 t 9 + t s ( ) ?? ? ?? ? , where t s is the setup time of the receiving device. symbol parameter conditions min typ max units t 7 cs /ld low to sck positive edge l 5 ns t 8 cs /ld high to sck positive edge l 5 ns t 9 sro propagation delay c load = 10pf l 26 ns t 10 clr pulse width low l 60 ns t 11 ldac pulse width low l 20 ns t 12 clr low to rflag low c load = 10pf (note 13) l 70 ns t 13 cs /ld high to rflag high c load = 10pf (note 13) l 60 ns sck frequency 50% duty cycle (note 14) l 25 mhz downloaded from: http:///
ltc2758 6 2758fa for more information www.linear.com/ltc2758 inl vs temperature dnl vs temperature gain error vs temperature bipolar zero error vs temperature inl vs reference voltage dnl vs reference voltage typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) v dd = 5v, v(r inx ) = 5v, t a = 25c, unless otherwise noted. inl vs output range code 0 65536 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.60.4 0.2 0 0.8 1.0 131072 196608 262143 2758 g01 0v to 10v range code 0 65536 C1.0 dnl (lsb) C0.8 C0.6 C0.4 C0.2 0.60.4 0.2 0 0.8 1.0 131072 196608 262143 2758 g02 0v to 10v range output range C2.5v to 2.5v C2.5v to 7.5v C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.40.2 0 0.6 0.8 1.0 0v to 5v C5v to 5v C10v to 10v 0v to 10v 2758 g03 temperature (c) C40 C20 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.40.2 0 0.6 0.8 1.0 0 20 80 60 40 85 2758 g04 +inl Cinl 0v to 10v range temperature (c) C40 C20 C1.0 dnl (lsb) C0.8 C0.6 C0.4 C0.2 0.40.2 0 0.6 0.8 1.0 0 20 80 60 40 85 2758 g05 +dnl Cdnl 0v to 10v range temperature (c) C40 C20 0 ge (lsb) 4 8 12 2016 24 28 32 0 20 80 60 40 85 2758 g06 0.25ppm/c typ 2.5v5v 10v 0v to 5v 0v to 10v C2.5v to 7.5v temperature (c) C40 C20 C16 bze (lsb) C12 C8 C4 40 8 12 16 0 20 80 60 40 85 2758 g07 5v10v 2.5v C2.5v to 7.5v 0.15ppm/c typ v(r in ) (v) C10 C2 C6 C4 C1.0 inl (lsb) C0.8 C0.6 C0.2C0.4 0.40.2 0 0.6 0.8 1.0 0 2 8 6 4 10 2758 g08 C8 +inl Cinl +inl Cinl 5v range v(r in ) (v) C10 C2 C6 C4 C1.0 dnl (lsb) C0.8 C0.6 C0.2C0.4 0.40.2 0 0.6 0.8 1.0 0 2 8 6 4 10 2758 g09 C8 +dnl Cdnl +dnl Cdnl 5v range downloaded from: http:///
ltc2758 7 2758fa for more information www.linear.com/ltc2758 typical performance characteristics settling full-scale step inl vs v dd dnl vs v dd logic threshold vs supply voltage supply current vs logic input voltage supply current vs update frequency mid-scale glitch (v dd = 3v) v dd = 5v, v(r inx ) = 5v, t a = 25c, unless otherwise noted. mid-scale glitch (v dd = 5v) multiplying frequency response vs digital code v dd (v) 2.5 3.5 4 C1.0 inl (lsb) C0.8 C0.6 C0.2C0.4 0.40.2 0 0.6 0.8 1.0 5 4.5 5.5 2758 g10 3 +inl Cinl 0v to 10v range v dd (v) 2.5 3.5 4 C1.0 dnl (lsb) C0.8 C0.6 C0.2C0.4 0.40.2 0 0.6 0.8 1.0 5 4.5 5.5 2758 g11 3 +dnl Cdnl 0v to 10v range all bits on all bits off frequency (hz) 100 1k 10k C140 attenuation (db) C100C120 C60C80 C40 C20 0 1m 100k 10m 2758 g12 0v to 5v output rangelt1468 output amplifier c feedback = 15pf d17d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 500ns/div cs /ld 5v/div gated settling waveform 100v/div (averaged) 2758 g13 lt1468 amp; c feedback = 20pf 0v to 10v stepv ref = C10v; span code = 0000 t settle = 1.8s to 0.0004% (18 bits) digital input voltage (v) 0 supply current (ma) 3 4 5 4 2758 g16 2 1 0 1 2 3 5 v dd = 5v clr , ldac , sdi, sck, cs /ld tied together v dd = 3v v dd (v) 2.5 0.5 logic threshold (v) 0.75 1 1.25 1.5 2 3 3.5 4 4.5 5 5.5 1.75 2758 g17 rising falling sck frequency (hz) 1 0.0001 supply current (ma) 0.001 0.01 0.1 1 10 100 v dd = 5v 100 10k 1m 100m 2758 g18 v dd = 3v alternating zero-scale and full-scale 500ns/div cs /ld 5v/div v out 5mv/div (averaged) 2758 g14 0v to 5v rangelt1468 output amplifier c feedback = 50pf rising major carry transition.falling transition is similar or better. 0.4nv ? s typ 500ns/div cs /ld 5v/div v out 5mv/div (averaged) 2758 g15 0v to 5v rangelt1468 output amplifier c feedback = 50pf rising major carry transition.falling transition is similar or better. 2nv ? s typ downloaded from: http:///
ltc2758 8 2758fa for more information www.linear.com/ltc2758 pin functions refa (pins 1, 2): feedback resistor for the dac a refer - ence inverting ampliier, and reference input for dac a. the 20k feedback resistor is connected internally from refa to r coma . for normal operation tie this pin to the output of the dac a reference inverting ampliier (see typical application). typically C5v; accepts up to 15v. pins 1 and 2 are internally shorted together. r coma (pin 3): virtual ground point for the dac a ref - erence ampliier inverting resistors. the 20k reference inverting resistors are connected internally from r ina to r coma and from r coma to refa, respectively (see block diagram). for normal operation tie r coma to the negative input of the external reference inverting ampliier (see typical application). ge adja (pin 4): gain adjust pin for dac a. this control pin can be used to null gain error or to compensate for reference errors. the gain change expressed in lsb is the same for any output range. see system offset and gain adjustments in the operation section. tie to ground if not used. r ina (pins 5, 6): input resistor for the dac a external reference inverting ampliier. the 20k input resistor is connected internally from r ina to r coma . for normal op - eration tie r ina to the external positive reference voltage (see typical application). either or both of these precision- matched resistor sets (each set comprising r inx , r comx and refx) may be used to invert positive references to provide the negative voltages needed by the dacs. typi - cally 5v; accepts up to 15v. pins 5 and 6 are internally shorted together. gnd (pins 7, 10, 15, 17, 18, 27, 30): ground; tie to ground.i out2as , i out2af (pins 8, 9): dac a current output complement sense and force pins. tie to ground via a clean, low-impedance path. these pins may be used with a precision ground buffer amp as a kelvin sensing pair (see the applications information section). cs /ld (pin 11): synchronous chip select and load input pin.sdi (pin 12): serial data input. data is clocked in on the rising edge of the serial clock (sck) when cs /ld is low. sck (pin 13): serial clock input. sro (pin 14): serial readback output. data is clocked out on the falling edge of sck. readback data begins clocking out after the last address bit a0 is clocked in. sro is an active output only when the chip is selected (i.e., when cs /ld is low). otherwise sro presents a high-impedance output in order to allow other parts to control the bus.v dd (pin 16): positive supply input; 2.7v v dd 5.5v. by - pass with a 0.1f low-esr ceramic capacitor to ground.clr (pin 19): asynchronous clear input. when this pin is low, all dac registers (both code and span) are cleared to zero. all dac outputs are cleared to zero volts. rflag (pin 20): reset flag output. an active low output is asserted when there is a power-on reset or a clear event. returns high when an update command is executed. dnc (pin 21): do not connect. m-span (pin 22): manual span control pin. m-span is used in conjunction with pins s2, s1 and s0 (pins 25, 24 and 23) to conigure all dacs for operation in a single, ixed output range. to conigure the part for manual-span use, tie m-span directly to v dd . the dac output range is then set via hardware pin strapping of pins s2, s1 and s0 (rather than through the spi port); and write and update commands have no effect on the active output span. to conigure the part for softspan use, tie m-span directly to gnd. the output ranges are then individually control - lable through the spi port; and pins s2, s1 and s0 have no effect. see manual span con?guration in the operation section. m- span must be connected either directly to gnd (softspan coniguration) or to v dd (manual-span coniguration). s0 (pin 23): span bit 0 input. in manual span mode (m- span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ixed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused.s1 (pin 24): span bit 1 input. in manual span mode (m- span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ixed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused. downloaded from: http:///
ltc2758 9 2758fa for more information www.linear.com/ltc2758 pin functions s2 (pin 25): span bit 2 input. in manual span mode (m- span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ixed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused. ldac (pin 26): asynchronous dac load input. when ldac is a logic low, all dacs are updated ( cs /ld must be high).i out2bf , i out2bs (pins 28, 29): dac b current output complement force and sense pins. tie to ground via a clean, low-impedance path. these pins may be used with a precision ground buffer amp as a kelvin sensing pair (see the applications information section). r inb (pins 31, 32): input resistor for the dac b external reference inverting ampliier. the 20k input resistor is connected internally from r inb to r comb . for normal op - eration tie r inb to the external positive reference voltage (see typical application). either or both of these precision- matched resistor sets (each set comprising r inx , r comx and refx) may be used to invert positive references to provide the negative voltages needed by the dacs. typi - cally 5v; accepts up to 15v. pins 31 and 32 are internally shorted together. ge adjb (pin 33): gain adjust pin for dac b. this control pin can be used to null gain error or to compensate for reference errors. the gain change expressed in lsb is the same for any output range. see system offset and gain adjustments in the operation section. tie to ground if not used.r comb (pin 34): virtual ground point for the dac b ref - erence ampliier inverting resistors. the 20k reference inverting resistors are connected internally from rinb to r comb and from r comb to refb, respectively (see block diagram). for normal operation tie r comb to the negative input of the external reference inverting ampliier (see typical application). refb (pins 35, 36): feedback resistor for the dac b reference inverting ampliier, and reference input for dac b. the 20k feedback resistor is connected internally from refb to r comb . for normal operation tie this pin to the output of the dac b reference inverting ampliier (see typical application). typically C5v; accepts up to 15v. pins 35 and 36 are internally shorted together. r ofsb (pins 37, 38): bipolar offset resistor for dac b. these pins provide the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r inb (pins 31, 32). pins 37 and 38 are internally shorted together. r fbb (pins 39, 40): dac b feedback resistor. for normal operation tie to the output of the i/v converter ampliier for dac b (see typical application). the dac output current from i out1b lows through the feedback resistor to the r fbb pins. pins 39 and 40 are internally shorted together. i out1b (pin 41): dac b current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampliier for dac b (see typical application). v osadjb (pin 42): dac b offset adjust pin. this voltage- control pin can be used to null unipolar offset or bipolar zero error. the offset change expressed in lsb is the same for any output range. see system offset and gain adjust - ments in the operation section. tie to ground if not used. v osadja (pin 43): dac a offset adjust pin. this voltage- control pin can be used to null unipolar offset or bipolar zero error. the offset change expressed in lsb is the same for any output range. see system offset and gain adjust - ments in the operation section. tie to ground if not used. i out1a (pin 44): dac a current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampliier for dac a (see typical application). r fba (pins 45, 46): dac a feedback resistor. for normal operation tie to the output of the i/v converter ampliier for dac a (see typical application). the dac output current from i out1a lows through the feedback resistor to the r fba pins. pins 45 and 46 are internally shorted together. r ofsa (pins 47, 48): bipolar offset resistor for dac a. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r ina (pins 5, 6). pins 47 and 48 are internally shorted together. downloaded from: http:///
ltc2758 10 2758fa for more information www.linear.com/ltc2758 block diagram timing diagram sdi sro hi-z cs /ld sck lsb 2758 td lsb t 2 t 9 t 8 t 5 t 7 1 2 31 32 t 6 t 1 ldac t 3 t 4 t 11 18 3 code registers span registers 31,32 33 34 35,36 37,38 39,40 41 28 42 r ofsb refb r inb sro sck sdi s2 s1 s0 m-span cs /ld ldac clr rflag ge adjb r comb i out1b 29 i out2bs i out2bf v osadjb r fbb 26 13 12 11 19 20 25 24 23 22 18 3 code registers span registers dac reg dac reg 5,6 4 3 1,2 47,48 45,46 44 8 9 43 r ofsa refa r ina ge adja r coma i out1a i out2as i out2af v osadja r fba dac a 18-bit with span select gnd 7, 10, 15, 17,18, 27, 30 14 v dd 16 input reg input reg input reg input reg dac reg dac reg dac b 18-bit with span select control and readback logic 2758 bd ltc2758 2.56m 2.56m 20k20k 20k20k power-on reset downloaded from: http:///
ltc2758 11 2758fa for more information www.linear.com/ltc2758 operation output ranges the ltc2758 is a dual, current-output, serial-input precision multiplying dac with selectable output ranges. ranges can either be programmed in software for maximum lexibility (each of the dacs can be programmed to any one of six output ranges) or hardwired through pin-strapping. two unipolar ranges are available (0v to 5v and 0v to 10v), and four bipolar ranges (2.5v, 5v, 10v and C2.5v to 7.5v). these ranges are obtained when an external precision 5v reference is used. the output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. the ranges can then be expressed: 0 to 1, 0 to 2, 0.5, 1, 2, and C0.5 to 1.5. manual span con?guration multiple output ranges are not needed in some applica - tions. to conigure the ltc2758 to operate in a single span without additional operational overhead, tie the m-span pin directly to v dd . the active output range for all dacs is then set via hardware pin strapping of pins s2, s1 and s0 (rather than through the spi port); and write and update commands have no effect on the active output span. see figure 1 and table 3. tie the m-span pin to ground for normal softspan operation.input and dac registers the ltc2758 has 5 internal registers for each dac, a total of 10 registers (see block diagram). each dac channel has two sets of double-buffered registers, one set for the code data, and one for the output range of the dac, plus one readback register. double buffering provides the ltc2758 m-span s2 s1 s0 2754 f01 cs /ld sdi sck v dd v dd 10v10v ?+ ?+ dac a dac b figure 1. using m-span to con?gure the ltc2758 for single-span operation (10v range shown) capability to simultaneously update the span (output range) and code, which allows smooth voltage transitions when changing output ranges. it also permits the simultaneous updating of multiple dacs. each set of double-buffered registers comprises an input register and a dac register. input register: the write operation shifts data from the sdi pin into a chosen input register. the input registers are holding buffers; write operations do not affect the dac outputs. dac register: the update operation copies the contents of an input register to its associated dac register. the contents of a dac register directly updates the associated dac output voltage or output range. note that updates always include both code and span register sets; but the values held in the dac registers will only change if the associated input register values have previously been altered via a write operation. downloaded from: http:///
ltc2758 12 2758fa for more information www.linear.com/ltc2758 operation data occupies the irst 18 bits of the 24-bit ield; and the span bits are the last four bits of the second data byte when checking the output range. in both cases, all other bits in the 24-bit data ield are illed by zeros. figure 2 shows the input and readback sequences.the data outputted by sro is always in the same position and sequence as the input data. note, however, that this means that the sro data shifts out one-half clock cycle earlier than the corresponding bit shifting in on sdi. for example, code bit d9, which is shifted in to sdi on the rising edge of sck clock 17, is clocked out of sro on the falling edge of clock 16. this allows d9 to be clocked to an external microprocessor on the rising edge of clock 17. for read commands, the requested data is shifted out of sro in the 3-byte (24-bit) data ield immediately after the command/address byte. there is no instruction-cycle latency for read commands; the data shifts out in the same instruction cycle in which it was requested. for non-read (i.e., write and/or update) commands, sro automatically shifts out the contents of the buffer that was acted upon in the preceding command. this rolling readback default mode of operation can dramatically re - duce the number of instruction cycles needed, since most commands can be veriied during subsequent commands with no additional overhead. a conceptual low diagram is shown in figure 3. table 1 shows, for each anteced - ent command, which register (readback pointer) will be copied into the readback register and outputted from sro during the following instruction cycle. span readback in manual span con?guration if a span dac register is chosen for readback, sro re - sponds by outputting the actual output span; this is true whether the ltc2758 is conigured for softspan (m-span tied to gnd) or manual span (m-span tied to v dd ). in softspan coniguration, sro outputs the span code from the span dac register (programmed through the spi port). in manual span coniguration, the active output range is controlled by pins s2, s1 and s0, so sro outputs the logic values of these pins. the span code bits s2, s1 and s0 always appear in the same order and positions in the sro output sequence; see figure 2. serial interface when the cs /ld pin is taken low, the data on the sdi pin is loaded into the shift register on the rising edge of the clock (sck pin). the loading sequence required for the ltc2758 is one byte consisting of a 4-bit command word (c3 c2 c1 c0) and a 4-bit address word (a3 a2 a1 a0), then three bytes (24 bits) of data. when writing a code, the code data is left (msb) justiied; so that the 24-bit data ield consists of 18 code bits fol - lowed by 6 dont-care bits. when writing an output range, the span data should oc - cupy the last 4 bits of the second data byte, ordered s3 through s0. figure 2 shows the sdi input word syntax for writing. when cs /ld is low, the sro pin (serial readback output) is an active output. the readback data begins after the command (c3-c0) and address (a3-a0) words have been shifted in to sdi. sro outputs a logic low from the falling edge of cs /ld until the readback data begins. when cs /ld is high, the sro pin presents a high imped - ance (three-state) output.ldac is an asynchronous update pin. when ldac is taken low, all dacs are updated with code and span data (data in the input buffers is copied into the dac buffers). cs /ld must be high during this operation; otherwise ldac is locked out and will have no effect. the use of ldac is functionally identical to the update all dacs serial input command. the codes for the command (c3-c0) are deined in table 1; table 2 deines the codes for the address (a3-a0). readback in addition to the code and span register sets, each dac has one readback register associated with it. every instruc - tion cycle, the contents of one of the on-chip registers is copied into a readback register and serially shifted out through the sro pin. readback data always appears in the 24-bit data ield, starting on the falling sck edge immediately after the last address bit is shifted in on sdi. when reading a code, code downloaded from: http:///
ltc2758 13 2758fa for more information www.linear.com/ltc2758 table 1. command codes code command readback pointer? current input word w 0 readback pointer? next input word w +1 c3 c2 c1 c0 0 0 1 0 write span dac n set by previous command input span register dac n 0 0 1 1 write code dac n set by previous command input code register dac n 0 1 0 0 update dac n set by previous command dac span register dac n 0 1 0 1 update all dacs set by previous command dac code register dac n 0 1 1 0 write span dac n update dac n set by previous command dac span register dac n 0 1 1 1 write code dac n update dac n set by previous command dac code register dac n 1 0 0 0 write span dac n update all dacs set by previous command dac span register dac n 1 0 0 1 write code dac n update all dacs set by previous command dac code register dac n 1 0 1 0 read input span register dac n input span register dac n 1 0 1 1 read input code register dac n input code register dac n 1 1 0 0 read dac span register dac n dac span register dac n 1 1 0 1 read dac code register dac n dac code register dac n 1 1 1 1 no operation set by previous command dac code register dac n C system clear C dac span register dac a C initial power-up or power interrupt C dac span register dac a codes not shown are reservedCdo not use table 2. address codes a3 a2 a1 a0 n 0 0 0 dac a 0 0 1 dac b 1 1 1 all dacs (note 1) codes not shown are reservedCdo not use. = dont care. note 1. if readback is taken using the all dacs address, the ltc2758 defaults to dac a. table 3. span codes s3 s2 s1 s0 span 0 0 0 unipolar 0v to 5v 0 0 1 unipolar 0v to 10v 0 1 0 bipolar C5v to 5v 0 1 1 bipolar C10v to 10v 1 0 0 bipolar C2.5v to 2.5v 1 0 1 bipolar C2.5v to 7.5v codes not shown are reservedCdo not use. = dont care. operation downloaded from: http:///
ltc2758 14 2758fa for more information www.linear.com/ltc2758 operation examples 1. load dac a with 0v to 10v range, output at zero volts; and dac b with 10v range, output at zero volts. note the dac outputs should change at the same time. a) cs /ld . clock sdi: 00101111 00000000 00000011 00000000 b) cs /ld span input register- range of dacs set to bipolar 10v. c) cs /ld . clock sdi: 00100000 00000000 00000001 00000000 d) cs /ld span input register- range of dac a set to unipolar 0v to 10v. e) cs /ld . clock sdi: 00111111 10000000 00000000 00xxxxxx f) cs /ld code input register- code of all dacs set to mid-scale. g) cs /ld . clock sdi: 00110000 00000000 00000000 00xxxxxx h) cs /ld code input register- code of dac a set to zero. i) cs /ld . clock sdi: 01001111 xxxxxxxx xxxxxxxx xxxxxxxx j) cs /ld update all dacs for both code and range. k) alternatively steps i and j could be replaced with ldac . 2. load dac b with 2.5v range with its output at zero volts. use readback to check input register contents before updating the dac output (i.e., before copying input register contents into dac registers). note that after power-on, the code in input registers is zero. a) cs /ld . clock sdi: 00110010 10000000 00000000 00xxxxxx b) cs /ld code input register- dac b set to mid-scale. c) cs /ld . clock sdi: 00100010 00000000 00000100 00000000 data out on sro: 10000000 00000000 00000000 veriies code input register- dac b set to mid-scale. d) cs /ld span input register- range of dac b set to bipolar 2.5v range. e) cs /ld . clock sdi: 10100010 xxxxxxxx xxxxxxxx xxxxxxxx data out on sro: 00000000 00000100 00000000 veriies span input register- dac b set to bipolar 2.5v range. cs /ld f) cs /ld . clock sdi: 01000010 xxxxxxxx xxxxxxxx xxxxxxxx g) cs /ld update dac b for both code and range h) alternatively steps f and g could be replaced with ldac . downloaded from: http:///
ltc2758 15 2758fa for more information www.linear.com/ltc2758 system offset and reference adjustmentsmany systems require compensation for overall system offset. this may be an order of magnitude or more greater than the offset of the ltc2758, which is so low as to be dominated by external output ampliier errors even when using the most precise op amps. the offset adjust pins v osadjx can be used to null unipolar offset or bipolar zero error. the offset change expressed in lsb is the same for any output range: ? v os lsb [ ] = Cv(v osadjx ) v(r inx ) ? 2048 a 5v control voltage applied to v osadjx produces ? v os = C2048 lsb in any output range, assuming a 5v reference voltage at r inx . in voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (these functions hold regardless of reference voltage.) ? v os = C( 1 / 128 )v osadjx [0v to 5v, 2.5v spans] ? v os = C( 1 / 64 )v osadjx [0v to 10v, 5v, C2.5v to 7.5v spans] ? v os = C( 1 / 32 )v osadjx [10v span] the gain error adjust pins ge adjx can be used to null gain error or to compensate for reference errors. the gain error change expressed in lsb is the same for any output range: ? ge = v(ge adjx ) v(r inx ) ? 2048 the gain-error delta is non-inverting for positive reference voltages. note that this pin compensates the gain by altering the inverted reference voltage v(refx). in voltage terms, the v(refx) delta is inverted and attenuated by a factor of 128. ? v(refx) = C( 1 / 128 )ge adjx the nominal input range of these pins is 5v; other volt - ages of up to 15v may be used if needed. however, do operation not use voltages divided down from power supplies; ref - erence-quality, low-noise inputs are required to maintain the best dac performance. the v osadjx pins have an input impedance of 1.28m. these pins should be driven with a thevenin-equivalent impedance of 10k or less to preserve the settling perfor - mance of the ltc2758. they should be shorted to gnd if not used. the ge adjx pins have an input impedance of 2.56m, and are intended for use with ixed reference voltages only. they should be shorted to gnd if not used. power-on reset and clear when power is irst applied to the ltc2758, all dacs power-up in unipolar 5v mode (s3 s2 s1 s0 = 0000). all internal dac registers are reset to 0 and the dac outputs initialize to zero volts. if the part is conigured for manual span operation, all dacs will be set into the pin-strapped range at the irst update command. this allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. when the clr pin is taken low, a system clear results. the dac buffers are reset to 0 and the dac outputs are all reset to zero volts. the input buffers are left intact, so that any subsequent update command (including the use of ldac ) restores the addressed dacs to their respective previous states. if clr is asserted during an instruction, i.e., when cs /ld is low, the instruction is aborted. integrity of the relevant input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. the rflag pin is used as a lag to notify the system of a loss of data integrity. the rflag output is asserted low at power-up, system clear, or if the supply v dd dips below approximately 2v; and stays asserted until any valid update command is executed. downloaded from: http:///
ltc2758 16 2758fa for more information www.linear.com/ltc2758 operation sdi c2 c1 c0 a3 a2 a1 a0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 c3 d0 x x x x x x d1 sdi c2 c1 c0 a3 a2 a1 a0 x x x x x x x x x x x x s3 s2 s1 s0 c3 x x x x x x x x sro 0 0 0 0 0 0 0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 0 d0 0 0 0 0 0 0 d1 command address 18-bit dac code 6 don?t-care command hi-z address 12 don?t-care span 2758 f02 8 don?t-care readback code write code write span sro 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 0 0 0 0 0 0 0 0 0 hi-z readback span 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cs /ld sck figure 2. serial input and output sequences downloaded from: http:///
ltc2758 17 2758fa for more information www.linear.com/ltc2758 operation sdi sro ... write code dac a read code input register dac a write code dac b read code input register dac b write span dac a read span input register dac a write span dac b read span input register dac b update all dacs read code dac register dac a ... 2758 f03 figure 3. rolling readback downloaded from: http:///
ltc2758 18 2758fa for more information www.linear.com/ltc2758 op amp selectionbecause of the extremely high accuracy of the 18-bit ltc2758, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 4 and 5 contain equations for evaluating the ef - fects of op amp parameters on the ltc2758s accuracy when programmed in a unipolar or bipolar output range. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. applications information table 5. easy-to-use equations determine op amp effects on dac accuracy in all output ranges (circuit of page 1). subscript 1 refers to output amp, subscript 2 refers to reference inverting amp. table 4. coef?cients for the equations of table 5 output range a1 a2 a3 a4 a5 5v 1.1 2 1 1 10v 2.2 3 0.5 1.5 5v 2 2 1 1 1.5 10v 4 4 0.83 1 2.5 2.5v 1 1 1.4 1 1 C2.5v to 7.5v 1.9 3 0.7 0.5 1.5 table 6 contains a partial list of ltc precision op amps recommended for use with the ltc2758. the easy-to-use design equations simplify the selection of op amps to meet the systems speciied error budget. select the ampliier from table 6 and insert the speciied op amp parameters in table 5. add up all the errors for each category to de - termine the effect the op amp has on the accuracy of the part. arithmetic summation gives an (unlikely) worst-case effect. a root-sum-square (rms) summation produces a more realistic estimate. a3?v os1 ?78.6 ? i b1 ?0.524 ? 0 a4?v os2 ?52.4 ? a4?i b2 ?0.524 ? a4? ( ) 5v v ref ( ) 5v v ref ( ) 66 a vol1 op amp v os1 (mv) i b1 (na) a vol1 (v/mv) v os2 (mv) i b2 (na) a vol2 (v/mv) v os1 ?12.1? i b1 ?0.0012 ?? a1? 0 0 0 inl (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 6 a vol1 ( ) 262 a vol2 ( ) 524 a vol1 ( ) 524 a vol1 ( ) 524 a vol2 ( ) 524 a vol2 v os1 ?3.1 ? i b1 ?0.00032 ?? a2? 0 0 0 dnl (lsb) ( ) 5v v ref ( ) 5v v ref a3?v os1 ?52.4 ? i b1 ?0.524 ?? 0 0 0 0 unipolar offset (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref v os1 ?52.4 ? i b1 ?0.0072 ? a5? v os2 ?104.8 ? i b2 ?1.048? bipolar gain error (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref bipolar zero error (lsb) unipolar gain error (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref v os1 ?52.4 ? i b1 ?0.0072 ? a5? v os2 ?104.8? i b2 ?1.048 ? table 6. partial list of ltc precision ampli?ers recommended for use with the ltc2758 with relevant speci?cations amplifier amplifier specifications v os v i b na a vol v/mv voltage noise nv/ hz current noise pa/ hz slew rate v/s gain bandwidth product mhz t settling with ltc2758 s power dissipation mw ltc1150 10 0.05 5600 90 0.0018 3 2.5 10ms 24 lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1012 25 0.1 2000 14 0.02 0.2 1 120 11.4 lt1097 50 0.35 2500 14 0.008 0.2 0.7 120 11 lt1468 75 10 5000 5 0.6 22 90 2.1 117 downloaded from: http:///
ltc2758 19 2758fa for more information www.linear.com/ltc2758 applications information op amp offset contributes mostly to dac output offset and gain error, and has minimal effect on inl and dnl. for example, consider the ltc2758 in unipolar 5v output range. (note that for this example, the lsb size is 19v.) an op amp offset of 35v will cause 1.8lsb of output offset, and 1.8lsb of gain error; but 0.4lsb of inl, and just 0.1lsb of dnl. while not directly addressed by the simple equations in tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. first, consult an op amps data sheet to ind the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 5 and calculate the tempera - ture-induced effects.for applications where fast settling time is important, ap - plication note 120, 1ppm settling time measurement for a monolithic 18-bit dac , offers a thorough discussion of 18-bit dac settling time and op amp selection.recommendations for dc or low-frequency applications, the ltc1150 is the simplest 18-bit accurate output ampliier. an auto-zero amp, its exceptionally low offset (10v max) and offset drift (0.01v/c) make nulling unnecessary. for swings above 8v, use an lt1010 buffer to boost the load current capability. the settling of auto-zero amps is a special case; see application note 120, 1ppm settling time measurement for a monolithic 18-bit dac , appendix e, for details. the lt1012 and lt1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. they are also excellent choices for the reference inverting ampliier in ixed-reference applications. for high speed applications, the ltc1468 settles in 2.1s. note that the 75v max offset will degrade the inl at the dac output by up to 0.9lsb. for high-speed applications demanding higher precision, the ampliier offset can be nulled with a digital potentiometer. the typical application on the last page shows a composite output ampliier that achieves fast settling (8s) and very low offset (3v max) without offset nulling. this circuit offers high open-loop gain (1000v/mv min), low input bias current (0.15na max), fast slew rate (25v/s min), and a high gain-bandwidth product (30mhz typ). the high speed path consists of an ltc6240, which is an 18mhz ultralow bias current ampliier, followed by an lt1360, a 50mhz fast-slewing ampliier which provides additional gain and the ability to swing to 10v at the output. compensation is taken from the output of the ltc6240, allowing the use of a much larger compensation capacitor than if taken after the gain-of-ive stage. an ltc2054 auto-zero ampliier senses the voltage at i out1 and drives the non-inverting input of the ltc6240 to eliminate the offset of the high speed path. the 100:1 attenuator and input ilter reduce the low frequency noise in this stage while maintaining low dc offset. precision voltage reference considerations much in the same way selecting an operational ampliier for use with the ltc2758 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. the output voltage of the ltc2758 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output volt - age error. there are three primary error sources to consider when selecting a precision voltage reference for 18-bit applications: output voltage initial tolerance, output voltage temperature coeficient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a references output voltage temperature coeficient affects not only the full-scale error, but can also affect the circuits inl and dnl performance. if a reference is chosen with a loose output voltage temperature coeficient, then the dac output voltage along its transfer characteristic will be very dependent on ambient conditions. minimizing the error due to reference temperature coeficient can be achieved by choosing a precision reference with a low output voltage temperature coeficient and/or tightly con - trolling the ambient temperature of the circuit to minimize temperature gradients. downloaded from: http:///
ltc2758 20 2758fa for more information www.linear.com/ltc2758 applications information table 7. partial list of ltc precision references recommended for use with the ltc2758 with relevant speci?cations reference initial tolerance temperature drift 0.1hz to 10hz noise lt1019a-5, lt1019a-10 0.05% max 5ppm/c max 12v p-p lt1236a-5, lt1236a-10 0.05% max 5ppm/c max 3v p-p lt1460a-5, lt1460a-10 0.075% max 10ppm/c max 20v p-p lt1790a-2.5 0.05% max 10ppm/c max 12v p-p ltc6652a-5 0.05% max 5ppm/c max 2.8ppm p-p ltc6655a-2.5 ltc6655a-5 0.025% max 2ppm/c max 0.25ppm p-p as precision dac applications move to 18-bit perfor - mance, reference output voltage noise may contribute a dominant share of the systems noise loor. this in turn can degrade system dynamic range and signal-to-noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. precision voltage references like the lt1236 or ltc6655 produce low output noise in the 0.1hz to 10hz region, well below the 18-bit lsb level in 5v or 10v full-scale systems. however, as the circuit bandwidths increase, iltering the output of the reference may be required to minimize output noise. grounding as with any high-resolution converter, clean grounding is important. a low-impedance analog ground plane is necessary, as are star grounding techniques. keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. the i out2 pins are of particular concern; inl will be degraded by the code-dependent currents carried by the i out2xf and i out2xs pins if voltage drops to ground are allowed to develop. the best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. alternatively, the pins may be routed to the star ground point if necessary; join the force and sense pins together at the part and route one trace for each channel of no more than 30 squares of 1oz copper. in the rare case in which neither of these alternatives is practicable, a force/sense ampliier should be used as a ground buffer (see figure 4). note, however, that the volt - age offset of the ground buffer amp directly contributes to the effects on accuracy speciied in table 5 under v os1 . the combined effects of the offsets can be calculated by substituting the total offset from i out1x to i out2xs for v os1 in the equations. downloaded from: http:///
ltc2758 21 2758fa for more information www.linear.com/ltc2758 applications information figure 4. optional circuits for driving i out2 from gnd with a force/sense ampli?er C + lt1468 dac a ltc2758 v ref 5v 2 6 3 6 i out1a 15pf i out2a r fba v osadja refa r coma r ina r ofsa v outa C + 6 1 2 3 i out2af i out2as 23 *schottky barrier diode zetex* bat54s lt1012 2758 f05 1000pf alternate amplifier for optimum settling time performance 6 1 2 3 89 89 C + lt1468 3 zetex bat54s 2 200 200 ? i out2as i out2af 150pf 32 dac b ?+ ge adja C + lt1012 47, 48 5, 6 43 1, 2 45, 46 44 8, 9 43 downloaded from: http:///
ltc2758 22 2758fa for more information www.linear.com/ltc2758 package description lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev ?) lx48 lqfp 0907 rev? 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 9.00 bsc a a 7.00 bsc 12 7.00 bsc 9.00 bsc 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note:1. package dimensions conform to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation, 0.50mm diameter5. drawing is not to scale see note: 4 c0.30 ? 0.50 r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 12 5.50 ref 7.15 ? 7.25 48 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a ? a 0.50 bsc 0.20 ? 0.30 1.30 min downloaded from: http:///
ltc2758 23 2758fa for more information www.linear.com/ltc2758 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/13 fixed r coma (pin 3) description updated typical application 8 24 downloaded from: http:///
ltc2758 24 2758fa for more information www.linear.com/ltc2758 ? linear technology corporation 2011 lt 0913 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2758 related parts typical application part number description comments ltc2757 single parallel 18-bit i out softspan dac 1lsb inl/dnl, software-selectable ranges, 7mm 7mm lqfp-48 package ltc1592 single serial 16-/14-/12-bit i out softspan dacs 1lsb inl, dnl, software-selectable ranges, 16-lead ssop package ltc2752 dual serial 16-bit i out softspan dac 1lsb inl/dnl, software-selectable ranges, 7mm 7mm lqfp-48 package ltc2754-12 quad serial 16-/12-bit i out softspan dacs 1lsb inl/dnl, software-selectable ranges, 7mm 8mm qfn-52 package ltc2704-12 quad serial 16-/14-/12-bit v out softspan dacs 1lsb inl/dnl, software-selectable ranges, integrated ampliiers references ltc6655 low drift precision buffered reference 0.025% max tolerance, 2ppm/c max, 0.25ppm p-p 0.1hz to 10hz noise lt1236 precision reference 0.05% max tolerance, 5ppm/c max, 3v p-p 0.1hz to 10hz noise lt1460 micropower precision series reference 0.075% max tolerance, 10ppm/c max, 20v p-p 0.1hz to 10hz noise lt1790 micropower low dropout reference 0.05% max tolerance, 10ppm/c max, 12v p-p 0.1hz to 10hz noise ltc6652 precision low drift low noise buffered reference 0.05% max tolerance, 5ppm/c max, 2.1ppm p-p 0.1hz to 10hz noise ampli?ers ltc1150 zero-drift op amp with internal capacitors 10v max offset, 16v high voltage operation, 1.8v p-p noise lt1012 precision op amp 25v max offset, 100pa max input current, 0.5v p-p noise, 380a supply current lt1001 precision op amp 25v max offset, 0.3v p-p noise, high output drive lt1468 single 16-bit accurate op amp 900ns settling, 90mhz gbw, 22v/s slew rate, 75v max offset composite ampli?er circuit achieves both fast settling and 18-bit precision with no adjustments 10k ltc2758 gnd v dd ldacclr r ina r ofsb r comb r inb refa, refb sdi spi bus sck cs/ld sro r ofsa ge adja ge adjb r coma v osadja v osadjb s2s0 m-span s1 i out1a i out2a i out1b i out2b r fba r fbb C+ 2758 ta02 ltc2054 C5v 5v 10k 8, 9 44 2619 43 4 4233 22 25 24 23 45, 46 out in 1, 2, 35, 36 3 28, 297, 10, 15, 17, 18, 27, 30 41 11 12 13 14 39, 40 1f 10k 1f 1k 10k 10k 1k C+ ltc6240 C5v 5v C15v 15v 100pf +C 10 5pf 4.02k 1k ?+ ltc2054 ?5v 5v 10k 1f 1f 1k 1k ?+ ltc6240 ?5v 5v ?15v 15v 100pf +? 10 5pf 4.02k 1k ltc1360 v outa v outb ltc1360 ?15v 15v 12v +? lt1012 100pf ltc6655-5 10f 0.1f 16 5, 6 37, 38 34 31, 32 47, 48 downloaded from: http:///

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